With a short channel effect caused by miniaturization of a semiconductor device, the threshold voltage of each MOS transistor has been lowered and an increase in subthreshold leakage current has been manifested. A characteristic not greater than the threshold voltage of each MOS transistor is of a subthreshold characteristic, and a leakage current at which a MOS silicon surface is in a weak inversion state, is called a subthreshold leakage current. As a method of reducing such a leakage current, a body bias technique has been well known. The subthreshold leakage current can be reduced by applying a predetermined body bias voltage to a semiconductor substrate (called “well” in the case of a CMOS) formed with MOS transistors.
A non-patent document 1 has described that a body bias voltage is switched between an active mode and a standby mode. In the active mode, an NMOS body bias voltage Vbn applied to a P well for each NMOS of a CMOS is set to a ground voltage Vss (0 volts) applied to an N type source of each NMOS. A PMOS body bias voltage Vbp applied to an N well for each PMOS of the CMOS is set to a source voltage Vdd (1.8 volts) applied to a P type source of each PMOS. In the standby mode that reduces a subthreshold leakage current, the NMOS body bias voltage Vbn applied to the P well is set to a negative voltage (−1.5 volts) corresponding to a reverse body bias with respect to the ground voltage Vss (0 volts) applied to the N type source of each NMOS of the CMOS. The PMOS body bias voltage Vbp applied to the N well is set to a positive voltage (3.3 volts) corresponding to a reverse body bias with respect to the source voltage (1.8 volts) applied to the P type source of each PMOS of the CMOS.
There has been a strong demand for speeding-up and low power consumption of an SRAM (Static Random Access Memory). There is provided a method in which lowering a source voltage to reduce power consumption of the SRAM is the simplest and large in effect. At a low source voltage, however, an operating margin necessary for the operation of each transistor is reduced and its operation becomes unstable.
With the foregoing in view, a technique for controlling a body bias voltage of each transistor constituting an SRAM cell according to write/read operations thereby to provide speeding-up at writing and reduce power consumption at reading has been disclosed in a patent document 1. In a manner similar to the patent document 1, a patent document 2 has disclosed that a body bias voltage is controlled according to write/read operations and a storage retention or holding operation to provide body bias voltages most suitable for the respective operations, thereby enhancing performance at the respective operations. Alternatively, a technique for controlling a body bias voltage of a SRAM memory cell at standby thereby to reduce a leakage current has been disclosed in a patent document 3.    [Non-patent document 1] Hiroyuki Mizuno et al, “A 18 μA-Standby-Current 1.8V 200 MHz Microprocessor with Self Substrate-Biased Data-Retention Mode”, 1999 IEEE International Solid-State Circuits Conference DIGEST OF TE CHNICAL PAPPERS, pp. 280-281, 468    [Patent Document 1] Japanese Patent Laid Open No. Hei 11(1999)-39879    [Patent Document 2] Japanese Patent Laid-Open No. 2004-349530    [Patent Document 3] Japanese Patent Laid-Open No. 2003-132683